Principal Engineer Verification

Your Role Key responsibilities in your new role Performs and supervises detailed Simulation, verification and validation of integrated circuits. Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Provide regression setup, debug of RTL and gate level netlist.…