Engineer-std cell layout
Hyderabad - Phoenix Aquilaonsitemid
Posted today · via Workday
About this role
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design and maintain standard cells layout for new DRAM products on new technology Lead the stdcells layout projects from initial spec definition to till PPA qualified library release Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Perform layout verification like LVS/DRC/Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
We compare your skills against the role requirements.
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in Hyderabad - Phoenix Aquila. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
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